1. Field of the Invention
The present invention relates to semiconductor memory devices and a method of manufacturing the same, and particularly to a semiconductor memory device including a junction field effect transistor and a capacitor, for example, a dynamic random access memory and a method of manufacturing the same.
2. Description of the Background Art
In recent years, the demand for semiconductor memory device has rapidly increased in accordance with the remarkable spread of information processing equipment such as computers. Functionally, a semiconductor memory device having a large-scale storage capacity and being capable of high-speed operation is demanded. Under such a background, technical development concerned with large scale integration, high response rate, or high reliability of semiconductor memory devices is in progress.
Semiconductor memory devices include those allowing random input thereto/output therefrom of storage information, which include DRAMs (Dynamic Random Access Memories). A DRAM generally includes a memory cell array which is a storage region storing a plurality of pieces of storage information and peripheral circuits necessary for input thereto and output therefrom from and to the outside.
FIG. 13 is a block diagram illustrating a general structure of a DRAM. Referring to FIG. 13, a DRAM 50 includes a memory cell array 51, a row and column address buffer 52, a row decoder 53 and a column decoder 54, a sense refresh amplifier 55, a data in buffer 56 and a data out buffer 57, and a clock generator 58. Memory cell array 51 is for storing data signals of storage information. Row and column address buffer 52 is for receiving from the outside an address signal A.sub.0 -A.sub.9 for selecting a memory cell which constitutes an unit storage circuit. Row decoder 53 and column decoder 54 are for designating a memory cell by decoding the address signal. Sense refresh amplifier 55 is for amplifying and reading the signal stored in the designated memory cell. Data in buffer 56 and data out buffer 57 are for data input/output. Clock generator 58 generates a clock signal to be a control signal to each unit.
A plurality of memory cells for storing unit storage information are arranged in a matrix manner in memory cell array 51 occupying a large area on a semiconductor chip. FIG. 14 is an equivalent circuit diagram of four bits of memory cells included in memory cell array 51. Memory cell array 51 includes a plurality of word lines WL extending parallel in the row direction and a plurality of bit line pairs BL, BL extending parallel in the column direction. Memory cells M are formed in the vicinity of crossings of word lines WL and bit lines BL, BL. The illustrated memory cell M includes one MOS (Metal Oxide Semiconductor) transistor Tr and one capacitor C. Specifically, each memory cell is illustrated as a so-called one transistor-one capacitor type memory cell. The structure of a memory cell of this type is simple, so that it can enhance the degree of integration of memory cell arrays and is widely used in DRAMs of large capacity. The structure in which a pair of bit lines BL, BL are arranged parallel in regard to a sense amplifier as illustrated in FIG. 14 is referred to as a folded bit line type.
Referring to FIG. 13, data is stored in memory cell array 51 of N (=n.times.m) bits. Address information concerned with the memory cell to/from which reading/writing is going to be performed is retained in row and column address buffer 52, and row decoder 53 selects a particular word line (selects one word line from n word lines) to couple m bits of memory cells through bit lines to sense refresh amplifier 55. Then, column decoder 54 selects a particular bit line (selects one bit line from m bit lines) to couple the sense refresh amplifier of one of them to an input/output circuit, and reading or writing is performed in accordance with a command from a control circuit.
Referring to FIG. 14, a gate electrode of a MOS transistor Tr is connected to a word line WL, a source/drain electrode is connected to an electrode of a capacitor C, and another source/drain electrode is connected to a bit line BL. On data writing, a prescribed voltage is applied to word line WL to render MOS transistor Tr conductive, so that an electric charge applied to bit line BL is stored in capacitor C. On data reading, a prescribed voltage is applied to word line WL to render MOS transistor Tr conductive, so that an electric charge stored in capacitor C is withdrawn through bit line BL.
In recent years, advancement of semiconductor memory devices is remarkable, and miniaturization of each of semiconductor device patterns formed in them has rapidly progressed as the degree of integration and density of them have become higher. There is a strong demand for a semiconductor memory device of a high speed, a small size, and a large capacity. In order to realize these requests, it has become indispensable to further miniaturize the pattern of each semiconductor element. Particularly, the above-described memory cell in a DRAM is a representative. It is necessary to reduce the occupied area of a semiconductor substrate by not only reducing the size of each single element such as a transistor and a capacitor but also reducing the size of a memory cell constituted with them. Various types of memory cell structures are being actively developed in order to reduce the occupied area in a memory cell region.
In a conventional 1-megabit DRAM, a capacitor and a transistor constituting a memory cell were arranged in a planar part of a main surface of a semiconductor substrate. However, it was necessary to reduce the occupied area of a semiconductor substrate for one memory cell in order to enhance the degree of integration from 1 megabit to 4 megabits, 16 megabits, and 64 megabits. Reduction of the area of a capacitor was limited because the capacitance value of the capacitor must be more than a certain value. The capacitance value must be at least approximately 40fF in order to prevent malfunctions of circuits, caused by generation of electron-hole pairs in a semiconductor substrate caused by alpha particles included in a package or the like of a DRAM, i.e. soft errors. On the other hand, in a channel region in an insulated gate field effect transistor, a short channel effect, which is an effect that reduction in a threshold voltage and increase in a change in the threshold voltage for the channel length are caused in accordance with reduction in the channel length, and a narrow channel effect, which is an effect that increase in the threshold voltage is caused by extension of a depletion layer under the channel region in the direction of the width in accordance with reduction in the channel width, are caused. Furthermore, a problem concerned with reliability is caused, which is of the characteristics of a transistor being degraded in a long period of time by hot carriers generated by impact ionization in the pinch-off region at the end of a drain region. It was difficult to make the channel length and the channel width not more than 1 .mu.m because of such problems in the channel region.
A one transistor-one capacitor dynamic memory cell in which a vertical-type transistor is formed in the sidewall part of a trench for a capacitor is disclosed in IEDM Technical Digest p. 714-717, Dec. 1-4, 1985, "A TRENCH TRANSISTOR CROSS-POINT DRAM CELL" in order to avoid occurrence of the problems as described above and attain higher density and higher degree of integration. According to the literature, a structure is disclosed, which is most advantageous in attempting reduction of the occupied area because all the memory cells in a DRAM are buried in trenches. FIG. 15 is a plan view illustrating such a DRAM, and FIG. 16 is a partial sectional view illustrating a cross sectional structure along line XVI--XVI in FIG. 15.
Referring to FIG. 15, n.sup.+ impurity regions 103 which serve as a plurality of bit lines and gate electrodes 105 which serve as a plurality of word lines are arranged crossing each other at right angles. Trenches 101 are formed at crossings of the bit lines and the word lines. Memory cells M are formed in trenches 101, respectively. Referring to FIG. 16, memory cells M isolated by an isolating oxide film 110 are formed on a main surface of a p-type silicon substrate 102. Each of the memory cells M includes a n channel MOS transistor and a capacitor. The n channel MOS transistor includes n.sup.+ impurity regions 103, 104 constituting drain/source regions, a channel region 106 provided between them, and a gate electrode 105 formed on channel region 106 with a gate oxide film 105a interposed therebetween. Channel region 106 is on the periphery of gate oxide film 105a formed on the main surface of silicon substrate 102 and exists along the sidewall part of the trench. The capacitor includes a capacitor electrode 120 formed to be connected to n.sup.+ impurity region 104 included in the n channel MOS transistor, a capacitor oxide film 130, and a p-type silicon substrate 102. Capacitor electrode 120 includes a polycrystalline silicon layer buried in the trench formed in p-type silicon substrate 102. n.sup.+ impurity region 104 is provided in a ring shape on the periphery of capacitor electrode 120. Gate electrode 105 included in the n channel MOS transistor includes a n.sup.+ polycrystalline silicon layer and serves as a word line.
As described, in the memory cell illustrated in FIG. 16, a vertical n channel MOS transistor is formed in the sidewall part of a trench provided for a capacitor. In other words, a capacitor and an insulated gate type field effect transistor are arranged in a trench, lined in a vertical direction. Accordingly, most of the capacitor region is arranged on the sidewall of a trench, and the whole of a channel region of the insulated gate field effect transistor is arranged only on the sidewall of the trench. A less area of the planar part of the main surface of the substrate is occupied by the n channel MOS transistor. As a result, enhancement of the degree of integration of the memory cells is attained. Maintenance of the performance of the transistor is attained by forming the channel region in the sidewall part of the trench, for example, without miniaturizing the transistor itself.
In the memory cell illustrated in FIG. 16, the area of the capacitor and the channel length of the insulated gate field effect transistor can be extended by forming deep the trench. Furthermore, capacitor electrode 120 serving as an information charge storing region is arranged inside the trench, so that it is less likely affected by electron-hole pairs, which are generated in the semiconductor substrate by alpha particles, and is strong against soft errors. Therefore, the capacitance value of the capacitor may be lower than that in the case where information charge storing region is arranged in the semiconductor substrate.
According to the structure of the memory cell illustrated in FIG. 16, the insulated gate field effect transistor is formed in the sidewall part of the trench. Therefore, it is very difficult to control the length of the gate in a manufacturing process. As a result, there is a possibility that the length of the gate in each memory cell varies largely. In the structure of the memory cell illustrated in FIG. 16, the length of the gate of the insulated gate field effect transistor varies in accordance with the depth of etching of p-type silicon substrate 102, the amount of etching of the polycrystalline silicon layer on formation of capacitor electrode 120, and so on. There was a problem that if the length of the gate varies largely as described above, the current driving capability of the insulated gate field effect transistor varies, and, as a result, the switching rate varies largely.
In addition, the structure of the memory cell illustrated in FIG. 16 is a so-called substrate/cell plate-type memory cell in which p-type silicon substrate 102 serves as a cell plate electrode. Therefore, in this structure, the noise of p-type silicon substrate 102 directly causes fluctuation of the potential of the cell plate, and the noise margin of the memory cell is reduced. Specifically, fluctuation of the difference between the potentials of storage node and the cell plate is reduced by the effect of the noise, so that there is a danger that the amount of charge stored in the capacitor is reduced. Furthermore, in the substrate/cell plate-type memory cell, it is not possible to apply a potential different from a prescribed potential of the substrate to the cell plate, so that it is not possible to adjust the potential of the cell plate to reduce the electric field strength on capacitor dielectric film 130.
It is reported in M. Kumanoya et al. IEEE Journal of Solid-State Circuits, vol. SC-20, No. 5, pp. 909-913, Oct. 1985 "A Reliable 1-Mbit DRAM with a Multi-Bit-Test Mode" that the electric field strength on the capacitor dielectric film is reduced by providing a potential Vcc/2 (2V), which is different from the substrate potential Vss (0V), to the cell plate (Vcc indicates the supply voltage, and the signal potentials of a high or "H" level and a low or "L" level are 4V and 0V, respectively), so that reliability of the memory cell is enhanced. Specifically, the capacitor dielectric film must withstand the electric field strength of 4V when the substrate potential Vss is provided to the cell plate, while it must withstand the electric field strength of 2V when Vcc/2 is provided to the cell plate. Accordingly, when the substrate potential is provided to the cell plate, the capacitor dielectric film must have a higher thickness, and the thick capacitor dielectric film is not preferred for attaining higher degree of integration of the DRAM.
In the structure of the memory cell illustrated in FIG. 16, the potential of the cell plate electrode becomes a negative potential which is applied to p-type silicon substrate 102, so that there was a problem that it is not possible to apply the above-described method in which the voltage applied to the capacitor dielectric film is Vcc/2.
On the other hand, a DRAM employing a junction field effect transistor is disclosed in U.S. Pat. No. 4,423,490. The U.S. Patent does not disclose a structure of a DRAM comprising a junction field effect transistor for attaining higher degree of integration and higher density.